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PD - 95879
AUTOMOTIVE MOSFET
Features
Designed to support Linear Gate Drive Applications 175C Operating Temperature Low Thermal Resistance Junction - Case Rugged Process Technology and Design Fully Avalanche Rated
IRF3305
HEXFET(R) Power MOSFET
D
VDSS = 55V RDS(on) = 8.0m
Description
Specifically designed for use in linear automotive applications this HEXFET Power MOSFET utilizes a rugged planar process technology and device design, which greatly improves the Safe Operating Area (SOA) of the device. These features, coupled with 175C junction operating temperature and low thermal resistance of 0.45C/W make the IRF3305 an ideal device for linear automotive applications.
G S
ID = 75A
Absolute Maximum Ratings
Parameter
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) ID @ TC = 100C Continuous Drain Current, VGS @ 10V ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current IDM
TO-220AB
Max.
140 99 75 560 330 2.2 20 W W/C V mJ A mJ -55 to + 175 C 300 (1.6mm from case ) 10 lbfyin (1.1Nym) A
Units
PD @TC = 25C Power Dissipation VGS EAS (Tested ) IAR EAR TJ TSTG Linear Derating Factor Gate-to-Source Voltage
EAS (Thermally limited) Single Pulse Avalanche Energyd Single Pulse Avalanche Energy Tested Value Avalanche CurrentA Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
h
470 860 See Fig.12a, 12b, 15, 16
g
Thermal Resistance
RJC RCS RJA Junction-to-Case
i
Parameter
Typ.
--- 0.50 ---
Max.
0.45 --- 62
Units
C/W
Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
i
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7/2/04
IRF3305
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff.
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units
55 --- --- 2.0 41 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.055 --- --- --- --- --- --- --- 100 21 45 16 88 43 34 4.5 7.5 3650 1230 450 4720 930 1490 --- --- 8.0 4.0 --- 25 250 200 -200 150 --- --- --- --- --- --- --- --- --- --- --- --- --- --- V V/C m V S A nA
Conditions
VGS = 0V, ID = 250A Reference to 25C, ID = 1mA VGS = 10V, ID = 75A VDS = VGS, ID = 250A VDS = 25V, ID = 75A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V ID = 75A VDS = 44V VGS = 10V VDD = 28V ID = 75A RG = 2.6 VGS = 10V Between lead,
e
nC
e e
ns
nH
6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V = 1.0MHz VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 44V, = 1.0MHz VGS = 0V, VDS = 0V to 44V
pF
f
Source-Drain Ratings and Characteristics
Parameter
IS ISM VSD trr Qrr ton
Notes:
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 57 130 75 A 560 1.3 86 190 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 75A, VGS = 0V TJ = 25C, IF = 75A, VDD = 28V di/dt = 100A/s
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
e
Coss eff. is a fixed capacitance that gives the same charging time max. junction temperature. (See fig. 11). as Coss while VDS is rising from 0 to 80% VDSS . Limited by TJmax, starting TJ = 25C, L = 0.17mH Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive RG = 25, IAS = 75A, VGS =10V. Part not avalanche performance. recommended for use above this value. This value determined from sample failure population. 100% Pulse width 1.0ms; duty cycle 2%. tested to this value in production. Coss eff. is a fixed capacitance that gives the R is measured at TJ of approximately 90C. same charging time as Coss while VDS is rising from 0 to 80% VDSS . Repetitive rating; pulse width limited by
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IRF3305
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
100
100
4.5V 60s PULSE WIDTH Tj = 175C
10 0.1 1 10 100
4.5V 60s PULSE WIDTH Tj = 25C
10 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
80
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current()
TJ = 25C 60 TJ = 175C 40
100.0
TJ = 175C
10.0
1.0
TJ = 25C VDS = 25V
20 VDS = 10V 380s PULSE WIDTH 0 0 20 40 60 80 100 120 140 ID, Drain-to-Source Current (A)
60s PULSE WIDTH
0.1 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance Vs. Drain Current
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IRF3305
7000 6000 5000 4000 3000 2000 1000 0 1 10 100 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
VGS, Gate-to-Source Voltage (V)
ID= 75A 16
VDS = 44V VDS= 28V
C, Capacitance (pF)
Ciss
12
8
Coss
4
Crss
0 0 40 80 120 160 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.0
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
TJ = 175C
100.0
OPERATION IN THIS AREA LIMITED BY R DS (on)
1000
100
100sec
10.0
TJ = 25C
1.0
10
1msec
1
VGS = 0V
0.1 0.0 0.4 0.8 1.2 1.6 2.0 2.4
Tc = 25C Tj = 175C Single Pulse 1 10
10msec DC 100 1000
0.1
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF3305
140 LIMITED BY PACKAGE 120
ID , Drain Current (A)
RDS(on) , Drain-to-Source On Resistance (Normalized)
2.5
ID = 75A
2.0
VGS = 10V
100 80 60 40 20 0 25 50 75 100 125 150 175 TC , Case Temperature (C)
1.5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Normalized On-Resistance Vs. Temperature
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05 0.02 0.01
R1 R1 J 1 2 R2 R2 R3 R3 3 C 3
0.01
J
Ri (C/W) i (sec) 0.1758 0.00045 0.228 0.0457 0.004565 0.01858
1
2
0.001
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE )
0.0001 1E-006 1E-005 0.0001 0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF3305
EAS, Single Pulse Avalanche Energy (mJ)
15V
2000
VDS
L
DRIVER
1600
ID 18A 26A BOTTOM 75A
TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
1200
A
0.01
800
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
400
0 25 50 75 100 125 150 175
Starting TJ, Junction Temperature (C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS
QGD
VGS(th) Gate threshold Voltage (V)
4.0
ID = 5.0A
3.5
VG
ID = 1.0A
ID = 250A
3.0
Charge
Fig 13a. Basic Gate Charge Waveform
2.5
2.0
L
0
1.5
DUT 1K
VCC
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
TJ , Temperature ( C )
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
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IRF3305
10000
Avalanche Current (A)
1000
Duty Cycle = Single Pulse
100
0.01 0.05
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax
10
0.10
1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
500
EAR , Avalanche Energy (mJ)
400
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A
300
200
100
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. 175 D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy Vs. Temperature
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IRF3305
Driver Gate Drive
D.U.T
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
RD
VDS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
D.U.T.
+
-VDD
Fig 18a. Switching Time Test Circuit
VDS 90%
10% VGS
td(on) tr t d(off) tf
Fig 18b. Switching Time Waveforms
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IRF3305
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
14.09 (.555) 13.47 (.530)
4.06 (.160) 3.55 (.140)
3X 1.40 (.055) 3X 1.15 (.045) 2.54 (.100) 2X NOTES:
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.92 (.115) 2.64 (.104)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB LY L OT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101]market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/04
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